Power supply noise is one of the most critical design challenges with high speed integrated circuits, and high speed interfaces in particular. In addition, there are numerous other circuits that are sensitive to power supply noise. These include sensitive analog circuits and delay paths, such as clock distribution circuits. Power supply noise affects these circuits in various ways; however, a critical problem is noise-induced jitter on clock signals and delay paths. For high speed interfaces, jitter reduces the effective window for capturing data, resulting in lower performance or higher error rates.
Previous attempts to solve this problem include the use of bypass capacitance. However, for many high speed circuits, adding bypass capacitance has limited usefulness because the amount of bypass capacitance that can be added to a modern circuit is limited because it consumes valuable area on a chip, thus increasing cost. Further, adding additional capacitance to the device package or board has limited effect because the inductance of the package and interconnect limits the effective frequency range that can be compensated by adding bypass capacitance. For modern packaging technology, the ability to filter out noise with on-package or on-board capacitors is limited to a few hundred megahertz. Unfortunately, high speed circuits are sensitive to the effects of noise up to multiple gigahertz. For circuits that are operating at very high frequencies, such as 6 Gigahertz (Ghz) or higher, they can easily create noise at sub-multiples of these frequencies. One of the major contributors to this noise is switching currents. Every time a gate or driver circuitry changes state, there is additional current flow due to charging/discharging capacitors as well as shoot-through currents caused by pullup and pulldown transistors being on at the same time. Noise on the power supplies can be caused by variations in this switching current, especially when the data has a series of transitions, followed by a series of data with few or no transitions. In such an instance, the current demanded by the circuits changes. This change in current can have frequency components that cannot be properly filtered out. In high-speed serial circuits, much of this current is dominated by the driver and related circuitry.
Another approach is to design circuitry that is insensitive, or more resistant to the negative effects of noise. Such circuits tend to be complex and with newer process generations, tend to be very sensitive to inherent process variations, in many cases causing more problems than they solve.
Another approach is for high-speed interfaces to use constant current drivers. Unfortunately, such constant current drivers consume a large amount of power and area on a semiconductor die.
Therefore, it would be desirable to have a way to shift the frequency of the problematic power supply noise in an integrated circuit.